1. Memory addresses

Memory Addresses

Word (Memory)

The storage cells of memory are of a regular and fixed size known as a word. In exams, take a word to be .

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Words in memory are arranged in groups known as blocks, which are different sizes depending on the system.

A memory address uniquely identifies a word and is composed of two fields:

  • : which block the word is in
  • : where the word is within the block Also referred to as the word field.
title: Example
Assume a memory consists of $2^{14}$ words and each block has $8$ words.
1. How many blocks does main memory have?
   $$
   	\text{blocks} = \frac{\text{number of words}}{\text{block size}} = \frac{2^{14}}{2^3} = 2^{11}
   $$
2. How many bits does an address have?
   We need to uniquely identify every word in the system.
   $$
   	\text{bits} = \lceil \log_2 (2^{14}) \rceil = 14 \text{ bits}
   $$
3. What are the field sizes of the address?
   $11$ bits to identify block, $3$ bits for the offset.
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2. Memory hierarchy

Memory hierarchy

Financial cost can be a limitation to creating the most efficient computer system. Memory can typical have a small size and low latency or a large size and high latency.

Naive approach: Exposed Hierarchy

One naive approach to memory hierarchy is to have all the memory components exposed to the processor. It is then the programmer’s responsibility to decide where to store data.

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Problems include that it requires complex load and store instructions in the instruction set. Programs will be competing against each other.

Better approach: implicit memory hierarchy

Complexities of the memory are hidden from the processor. The hardware handles whether data is stored in fast or slow memory depending on usage patterns.

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The processor will see fast memory as long as hardware keeps the required data within the cache. But the processor needs to handle different latencies on the fly (sometimes data will come in fast, sometimes slow)

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3. Effective access time

Caches

The processor sends an access request for a particular address to the cache. If we get a then the data for the address is in the cache and we can immediately return it.

If we get a then the data for the address is not in the cache, so the request is passed to the main memory (causing high latency), the memory returns data to the processor via the cache. We can choose to retain this data using a number of strategies including spacial locality, temporal locality, and sequential locality.

Effective Access Time

Hit ratio

Hit ratio is the fraction of hits to total attempts, $HR = \frac{\text{hits}}{\text{hits} + \text{misses}}$.

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Miss ratio

Miss ratio is the fraction of misses to total attempts, $HR = \frac{\text{misses}}{\text{hits} + \text{misses}}$.

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Effective Access Time

The Effective Access Time is the average time it takes to access something in memory: ?

Our aim is to reduce the effective time as much as possible.

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Overlapped access

Overlapped access

With cache, access can also be overlapped: the cache is checked in parallel with checking main memory. If the address is not found in the cache, there is slightly less of a penalty. However, this requires more advanced hardware and more power. With overlapped access, the effective access time becomes:

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4. Direct-mapped cache

Basic Cache

On a request from the processor for the data in memory address , we search the tags in cache:

  • is a tag
    1. Return data.
  • is not a tag
    1. Read data at address from memory.
    2. Return data.
    3. Select an address in the cache to hold and its data (according to replacment policy).
    4. Store in tag with data.

We use a number of approaches to organise the cache described over the next few topics, including this one.

Direct-mapped cache

Direct-mapped cache

In direct-mapped cache, each block in memory maps to a **single**, **specific** cache block.

For a direct mapped cache consisting of blocks: ?

  • Block of main memory maps to cache block .

To find out which block actually resides in a cache block at any given time we use a tag field which distinguishes one memory block from another.

A direct-mapped cache address is composed of the following: ?

  • The : number of bits required to address all cache blocks.
  • The : the number of bits required to address all words within a block.
  • The : the number of bits left over after the block and offset. Formatted as such: (, , ).
title: Remember the order: $\color{blue}\textsf{tag}$, $\color{red}\textsf{block}$, $\color{green}\textsf{word}$
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title: Example 1
![](https://git.is.horse/insert/university/obsidian-notes/-/raw/9d95afcbbdb7a4c77ca9f62b32e35c6f31e269e7/University/Year%201/Semester%201/4CCS1CS1%20Computer%20Systems%201/Week%209.%20Memory%20hierarchy%20and%20cache%20systems/Diagrams/Pasted%20image%2020211206123621.png)
title: Example 2
![](https://git.is.horse/insert/university/obsidian-notes/-/raw/9d95afcbbdb7a4c77ca9f62b32e35c6f31e269e7/University/Year%201/Semester%201/4CCS1CS1%20Computer%20Systems%201/Week%209.%20Memory%20hierarchy%20and%20cache%20systems/Diagrams/Pasted%20image%2020211206123733.png)
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5. Fully-associative cache

Fully-associative cache

Fully-associative cache

Instead of placing memory blocks in specific cache locations based on memory address, in a fully-associative cache, we can allow a block to go anywhere in cache.

A fully-associative cache address is composed of two fields: ?

  • the tag field: the block of main memory
  • the offset field: the position of the word within the block

In fully-associative caches, we may have to search the entire cache to find a particular tag which is an expensive process. In a direct-mapped cache, the search is fast as there is only one location where a particular address can be stored, so there is no search needed.

  • However, direct-mapped cache is overly rigid. Say the addresses were 000000 then 110000 then 000000 then 110000. In this case, the addresses map to different memory blocks but the same cache block.
  • We would be constantly removing and adding the same blocks to the cache (thrashing) even though we are only accessing two blocks which is an expensive process.
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title: Example 1
![](https://git.is.horse/insert/university/obsidian-notes/-/raw/9d95afcbbdb7a4c77ca9f62b32e35c6f31e269e7/University/Year%201/Semester%201/4CCS1CS1%20Computer%20Systems%201/Week%209.%20Memory%20hierarchy%20and%20cache%20systems/Diagrams/Pasted%20image%2020211206123857.png)
title: Example 2
![](https://git.is.horse/insert/university/obsidian-notes/-/raw/9d95afcbbdb7a4c77ca9f62b32e35c6f31e269e7/University/Year%201/Semester%201/4CCS1CS1%20Computer%20Systems%201/Week%209.%20Memory%20hierarchy%20and%20cache%20systems/Diagrams/Pasted%20image%2020211206123921.png)
title: Example 3
![](https://git.is.horse/insert/university/obsidian-notes/-/raw/9d95afcbbdb7a4c77ca9f62b32e35c6f31e269e7/University/Year%201/Semester%201/4CCS1CS1%20Computer%20Systems%201/Week%209.%20Memory%20hierarchy%20and%20cache%20systems/Diagrams/Pasted%20image%2020211206123943.png)
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6. Set-associative cache

Set-associative cache

Set-associative cache

Set-associative cache combines ideas of direct-mapped and fully-associative cache. The cache is divided into contiguous equal-sized sets.

A -way set-associative cache has multiple sets of $n$ blocks.

In a set-associative cache, each address maps to only one set: $$MM \text{ block number } \% \text{ number of sets}$$

A set-associative address is composed of the following: ?

  • uniquely identifies which main memory block is in the cache (in combination with the set)
  • uniquely identifies which set in the cache
  • uniquely identifies which word in the block

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title: Example 1: 4-way set-associative cache
![](https://git.is.horse/insert/university/obsidian-notes/-/raw/9d95afcbbdb7a4c77ca9f62b32e35c6f31e269e7/University/Year%201/Semester%201/4CCS1CS1%20Computer%20Systems%201/Week%209.%20Memory%20hierarchy%20and%20cache%20systems/Diagrams/Pasted%20image%2020211206130008.png)
title: Example 2: 4-way set-associative cache
![](https://git.is.horse/insert/university/obsidian-notes/-/raw/9d95afcbbdb7a4c77ca9f62b32e35c6f31e269e7/University/Year%201/Semester%201/4CCS1CS1%20Computer%20Systems%201/Week%209.%20Memory%20hierarchy%20and%20cache%20systems/Diagrams/Pasted%20image%2020211206130024.png)
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7. Replacement policies

Replacement policies

Replacement Policy

With associative caches, a replacement policy is required when deciding which block to remove from a **full cache**. The block to be removed is called the **victim block**.

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In most domains, the optimal replacement policy is not possible.

LRU

If we want to optimise for temporal locality we will want to kepe the most recently used blocks in the cache and remove blocks that have not been used for a long time.

We can use least-recently used (LRU) algorithm to keep track of the last time each cache block was accessed. The victim block is then the block which has been unused for the longest period of time. The LRU algorithm is complex; we have to maintain an access history for each block.

FIFO

A First-In First-Out (FIFO) policy is a popular and simple cache replacement policy. The block that has been in cache the longest is the victim block.

There is still a small overhead of keeping track of when things were added.

Random

A random policy is where we select a victim block at random and replace it with a new block. There is no overhead but we are equally as likely to remove the best and worst blocks.

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