1. Designing ISAs

Designing ISAs

There are different factors to consider when looking at different ISAs:

1. Instruction length: number of bits per instruction Are instructions short, long or variable?
2. Memory organisation: is memory byte- or word- addressable
3. No. of (explicit) operands per instruction. We could use a stack or one or more registers, we also need to consider how many addressable registers there are.
4. Addressing modes: is there direct, indirect or indexed addressing?
5. Type, size and location of operands.
6. Types of operations available. What can the ISA actually perform?

When choosing an ISA, we care about:

• main memory space occupied by a program
• instruction complexity and bit length
• total number of instructions in set

System clock

A system clock is used to synchronise all internal components, the clock outputs a steady high-frequency signal.

• A fixed number of clock cycles are required to carry each data movement or computational operation.

• Clock frequency

  The clock frequency, measured in Hertz, determines the speed with which all operations are carried out. Clock cycle time is the reciprocal of frequency.

  $$t_c=\frac{1}{f_c}$$

  A $800\text{ MHz}$ clock has a cycle time of $t_c=1.25\text{ ns}$.

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• The CPU time required to run a program is given by the general performance equation: $$T=\frac{\text{seconds}}{\text{program}}=\frac{\text{instructions}}{\text{program}}\times \frac{\text{avg. cycles}}{\text{instruction}}\times \frac{\text{seconds}}{\text{cycle}}$$ We can improve CPU throughput if we reduce:
  1. Number of instructions per program.
  2. Number of cycles per instruction.
  3. Number of seconds per clock cycle.

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2. Endianness

Endianness

Byte ordering

Byte ordering, or endianness, is the order in which we store bytes in memory and process them.

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Say we have a two-byte integer, we can choose where the least and most significant byte is stored:

• Big-endian

  Big-endian machines are where we store the most signfiicant byte followed by the least significant byte.

  It is more natural. The sign of the number can be determined by looking at the byte at address offset $0$. Strings and integers are stored in the same order.

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• Little-endian

  Little-endian machines are where we store the least significant byte followed by the most significant byte.

  Makes it easier to place values on non-word boundaries. Conversion from a 16-bit integer address to a 32-bit one does not require any arithmetic.

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Suppose we have the hex number $12345678$, the big / small endian arrangements of the bytes are:

Address	$00$	$01$	$10$	$11$
Big Endian	$12$	$34$	$56$	$78$
Little Endian	$78$	$56$	$34$	$12$

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3. Register Architectures

Register Architectures

Next consideration for the ISA is how the CPU will store data, there are different trade-offs involved in picking different types of architectures, including but not limited to the simplicity and cost of hardware design, execution speed and ease of use.

We can choose from the following main architectures:

1. Stack architecture

   Stack architecture: Instructions and operands are implicitly taken from the stack. A stack cannot be accessed randomly.

   Stack machines use one- and zero- operand instructions. All instructions implicitly operate on elements at the top of the stack.

   • Push X and Pop X instructions require a single memory address operand.
   • Binary instructions (such as Add, Mult) use the top two items in the stack.

   When working with stack architectures, arithmetic expressions should be structured with postfix notation ($Z=XY+$ as opposed to infix notation, $Z=X+Y$).

   Parentheses are not needed to find order of operations, $Z=(X\cdot Y)+(W\cdot U)$ can be represented as $Z=XY\cdot WU\cdot +$ in postfix notation, and could generate instructions such as:

   Push X
   Push Y
   Mult
   Push W
   Push U
   Mult
   Add
   Pop Z
   

   The result of each binary operation is stored at the top of the stack.

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2. Accumulator architecture

   Accumulator architecture: one operand of a binary operation is implicitly in the accumulator. (One operand is in memory, causing bus traffic.)

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3. General purpose register architecture

   General purpose register (GPR) architecture: registers can be used instead of memory. Faster than the accumulator architecture but results in longer instructions. This is how most systems today are designed.

   There are three types of GPR system:

   1. Memory-memory where two or three operands may be in memory.
   2. Register-memory where at least one operand must be in a register.
   3. Load-Store where no operands may be in memory.

   The number of operands and the number of available registers directly affects instruction length.

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4. Instruction Types

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5. Addressing

Addressing

Different addressing modes specify where an operand is located, can be any of: a constant, a register, or a memory location.

Effective address

The effective address is the actual location of an operand.

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Certain addressing modes allow us to dynamically determine this address.

Types of addressing:

• Immediate: the data is part of the instruction.
• Direct: address of the data is given in the instruction.
• Register: data located in register.
• Indirect: address of address of data is given.
• Register indirect: register stores address of the address of data.
• Indexed: uses a register (implictly or explicitly) as an offset, which is added to the address in the operand to determine the effective address of the data.
• Based: similar to indexed, except that a base register is used instead of an index register. A base register holds a base address which is used to displace the given address, think of the given address (in the instruction) as a relative address to the base address. Meanwhile an index register holds the offset relative to the address given in the instruction.
• Stack: the operand is assumed to be on the top of the stack.

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6. Pipelining

Pipelining

Instruction-level pipelining

Some CPUs perform instruction-level pipelining where they divide the [[FDE Cycle]] into smaller steps, and then execute these steps in parallel.\

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Consider an FDE cycle broken down into 6 stages:

1. Fetch instruction
2. Decode opcode
3. Calculate effective address of operands
4. Fetch operands
5. Execute instruction
6. Store result

These can be used in order in a six-stage pipeline. For every clock cycle, one small step is carried out and the stages are overlapped.

Theoretical Speed-up

The theoretical speed-up offered by a pipeline can be found as follows:

• Each instruction represents a task, $T$, in the pipeline.
• Let $N$ be the number of tasks (instructions) in the program.
• Let $t_p$ be the time per stage.
• Let $K$ be the number of stages in the pipeline.
• The first task $T_1$ requires $K{t}_p$ time to complete.
• The remaining $(N-1)$ tasks emerge from the pipeline one per cycle.
• So the total time to complete the remaining tasks is $(N-1)t_p$.

The time to complete $N$ tasks using a $K$-stage pipeline is:

$$\begin{array}{rl}T& =K{t}_p+(N-1)t_p\\ & =(K+N-1)t_p\end{array}$$

To compute the speed gain, we compare $T$ with the time taken to run the same program without pipelining, the time taken to run one task without pipelining is $K{t}_p$, hence we can find the time to do $N$ tasks to be $T^{\prime }=NK{t}_p$.

The fractional speed up is then given by:

$$S=\frac{T^{\prime }}{T}=\frac{NK{t}_p}{(K+N-1)t_p}$$

If we take the limit as $N\to \infty$ then $(K+N-1)\to N$. This results in a theoretical speedup of:

$$S_{\infty }=\frac{K{t}_p}{t_p}=K$$

These equations assume that:

• the architecture supports fetching instructions and data in parallel
• the pipeline can be kept filled at all times

Pipeline hazards are thongs that can cause a pipeline to stall, or be flushed for any reason such as: Resource conflicts, data dependencies, or conditional branching.

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