3. Register Architectures

Register Architectures

Next consideration for the ISA is how the CPU will store data, there are different trade-offs involved in picking different types of architectures, including but not limited to the simplicity and cost of hardware design, execution speed and ease of use.

We can choose from the following main architectures:

1. Stack architecture

   Stack architecture: Instructions and operands are implicitly taken from the stack. A stack cannot be accessed randomly.

   Stack machines use one- and zero- operand instructions. All instructions implicitly operate on elements at the top of the stack.

   • Push X and Pop X instructions require a single memory address operand.
   • Binary instructions (such as Add, Mult) use the top two items in the stack.

   When working with stack architectures, arithmetic expressions should be structured with postfix notation ($Z=XY+$ as opposed to infix notation, $Z=X+Y$).

   Parentheses are not needed to find order of operations, $Z=(X\cdot Y)+(W\cdot U)$ can be represented as $Z=XY\cdot WU\cdot +$ in postfix notation, and could generate instructions such as:

   Push X
   Push Y
   Mult
   Push W
   Push U
   Mult
   Add
   Pop Z
   

   The result of each binary operation is stored at the top of the stack.

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2. Accumulator architecture

   Accumulator architecture: one operand of a binary operation is implicitly in the accumulator. (One operand is in memory, causing bus traffic.)

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3. General purpose register architecture

   General purpose register (GPR) architecture: registers can be used instead of memory. Faster than the accumulator architecture but results in longer instructions. This is how most systems today are designed.

   There are three types of GPR system:

   1. Memory-memory where two or three operands may be in memory.
   2. Register-memory where at least one operand must be in a register.
   3. Load-Store where no operands may be in memory.

   The number of operands and the number of available registers directly affects instruction length.

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